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march 2011 ? 2011 fairchild semiconductor corporation www.fairchildsemi.com fl7930 ? rev. 1.0.0 fl7930 ? single-stage flyback and bou ndary-mode pfc controller for lighting fl7930 single-stage flyback and boundary-mode pfc controller for lighting features ? additional pfc-ready function (fl7930c only) ? input-voltage-absent-detection circuit ? maximum switching frequency limitation ? internal soft-start with overshoot prevention ? internal total harmonic distortion (thd) optimizer ? precise adjustable output over-voltage protection ? additional ovp detection pin (fl7930b only) ? open-feedback protection and disable function ? zero-current detector ? 150s internal startup timer ? mosfet over-current protection (ocp) ? under-voltage lockout with 3.5v hysteresis ? low startup and o perating current ? totem-pole output with high state clamp ? +500/-800ma peak gate drive current ? 8-pin small outline package (sop) applications ? ballast ? general led lighting ? industrial, commercial, and residential fixtures ? outdoor lighting: street, roadway, parking, construction and ornamental led lighting fixtures description the fl7930 is an active power factor correction (pfc) controller for low-to high-powe r lumens applications that operate in critical conduction mode (crm). it uses a voltage-mode pwm that compares an internal ramp signal with the error amplifier output to generate a mosfet turn-off signal. because the voltage-mode crm pfc controller does not need rectified ac line voltage information, it saves the power loss of an input voltage sensing network necessary for a current-mode crm pfc controller. fl7930 provides over-voltage, open-feedback, over- current, input-voltage-absent detection, and under- voltage lockout protections. the fl7930 can be disabled if the inv pin volt age is lower than 0.45v and the operating current decreases to a very low level. using a new variable on-time control method, thd is lower than the conventional crm boost pfc ics. the fl3930b provides an addi tional ovp pin that can be used to shut down the boost power stage when output voltage exceeds ovp level due to damaged resistors connected at the inv pin. the fl7930c provides a pfc-ready pin can be used to trigger other power stages when pfc output voltage reaches the proper level (with hysteresis). ordering information part number operating temperature range top mark package packing method fl7930bm -40 to +125c fl7930b 8-lead small outline package (sop) rail fl7930bmx tape & reel FL7930CM fl7930c rail FL7930CMx tape & reel
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fl7930 ? rev. 1.0.0 2 fl7930 ? single-stage flyback and bou ndary-mode pfc controller for lighting application diagrams figure 1. typical boost pfc application for fl7930b cs 8 zcd inv comp ovp gate gnd vcc 7 6 5 1 2 3 4 fl7930b c hf c f1 c f2 figure 2. typical application of single-stage flyback converter for fl7930b ac input dc output line filter 1 7 6 8 5 3 4 2 fl7930c comp inv v cc out gnd zcd cs rdy v cc pfc ready figure 3. typical boost pfc application for fl7930c
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fl7930 ? rev. 1.0.0 3 fl7930 ? single-stage flyback and bou ndary-mode pfc controller for lighting internal block diagram figure 4. functional bl ock diagram for fl7930b figure 5. functional bl ock diagram for fl7930c
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fl7930 ? rev. 1.0.0 4 fl7930 ? single-stage flyback and bou ndary-mode pfc controller for lighting pin configuration figure 6. pin configurations (top view) pin definitions pin # name description 1 inv this pin is the inverting input of the error amplifier. the output vo ltage of the boost pfc converter should be resistively divided to 2.5v. 2 ovp fl7930b : this pin is used to detect pfc output ove r-voltage when inv pin information is not correct. rdy fl7930c : this pin is used to detect pfc output-voltage reaching a pre-determined value. when output voltage reaches 89% of rated output voltage, this pin is pulled high, which is an (open-drain) output type. 3 comp this pin is the output of t he transconductance error amplif ier. components for the output voltage compensation should be connected between this pin and gnd. 4 cs this pin is the input of the ov er-current protection comparator. the mosfet current is sensed using a sensing resistor and the resulting voltage is applied to this pin. an internal rc filter is included to filter switching noise. 5 zcd this pin is the input of the zero -current detection block. if the voltage of this pin goes higher than 1.5v, then goes lower than 1.4v, the mosfet is turned on. 6 gnd this pin is used for the ground potential of all the pins. for proper oper ation, the signal ground and the power ground should be separated. 7 out this pin is the gate drive output. the peak sour cing and sinking current levels are +500ma and -800ma, respectively. for proper operation, the stray inductance in the gate driving path must be minimized. 8 vcc this is the ic supply pin. ic current and mosfet drive current are supplied using this pin.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fl7930 ? rev. 1.0.0 5 fl7930 ? single-stage flyback and bou ndary-mode pfc controller for lighting absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and stressi ng the parts to these levels is not recommended. in addition, extended exposure to stresses above the recomm ended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cc supply voltage v z v i oh , i ol peak drive output current -800 +500 ma i clamp driver output clamping diodes v o >v cc or v o <-0.3v -10 +10 ma i det detector clamping diodes -10 +10 ma v in error amplifier input, output, ovp input, zcd, rdy, and ovp pins (1) -0.3 8.0 v cs input voltage (2) -10 6 t j operating junction temperature +150 c t a operating temperature range -40 +125 c t stg storage temperature range -65 +150 c esd electrostatic discharge capability human body model, jesd22-a114 2.5 kv charged device model, jesd22-c101 2.0 notes: 1. when this pin is supplied by external power sources by accident, its maximum allowable current is 50ma. 2. in case of dc input, acceptable input range is -0.3v~ 6v: within 100ns -10v~6v is acceptable, but electrical specifications are not guarant eed during such a short time. thermal impedance symbol parameter min. max. unit ? ja thermal resistance, junction-to-ambient ( 3 ) 150 c/w note: 3. regarding the test environment and pcb type, please refer to jesd51-2 and jesd51-10.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fl7930 ? rev. 1.0.0 6 fl7930 ? single-stage flyback and bou ndary-mode pfc controller for lighting electrical characteristics v cc = 14v, t a = -40c to +125c, unless otherwise specified. symbol parameter condition min. typ. max. unit v cc section v start start threshold voltage v cc increasing 11 12 13 v v stop stop threshold voltage v cc decreasing 7.5 8.5 9.5 v hy uvlo uvlo hysteresis 3.0 3.5 4.0 v v z zener voltage i cc =20ma 20 22 24 v v op recommended operating range 13 20 v supply current section i start startup supply current v cc =v start -0.2v 120 190 a i op operating supply current out put not switching 1.5 3.0 ma i dop dynamic operating supply current 50khz, c i =1nf 2.5 4.0 ma i opdis operating current at disable v inv =0v 90 160 230 a error amplifier section v ref1 voltage feedback input threshold1 t a =25c 2.465 2.500 2.535 v ? v ref1 line regulation v cc =14v~20v 0.1 10.0 mv ? v ref2 temperature stability of v ref1 (4) 20 mv i ea,bs input bias current v inv =1v~4v -0.5 0.5 a i eas,sr output source current v inv =v ref -0.1v -12 a i eas,sk output sink current v inv =v ref +0.1v 12 a v eah output upper clamp voltage v inv =1v, v cs =0v 6.0 6.5 7.0 v v eaz zero duty cycle output voltage 0.9 1.0 1.1 v g m transconductance (4) 90 115 140 mho maximum on-time section t on,max1 maximum on-time programming 1 t a =25c, v zcd =1v 35.5 41.5 47.5 s t on,max2 maximum on-time programming 2 t a =25c, i zcd =0.469ma 11.2 13.0 14.8 s current-sense section v cs current-sense input threshold voltage limit 0.7 0.8 0.9 v i cs,bs input bias current v cs =0v~1v -1.0 -0.1 1.0 a t cs,d current-sense delay to output (4) dv/dt=1v/100ns, from 0v to 5v 350 500 ns continued on the following page?
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fl7930 ? rev. 1.0.0 7 fl7930 ? single-stage flyback and bou ndary-mode pfc controller for lighting electrical characteristics v cc = 14v, t a = -40c to +125c, unless otherwise specified. symbol parameter condition min. typ. max. unit zero-current detect section v zcd input voltage threshold (4) 1.35 1.50 1.65 v hy zcd detect hysteresis (4) 0.05 0.10 0.15 v v clamph input high clamp voltage i det =3ma 5.5 6.2 7.5 v v clampl input low clamp voltage i det = -3ma 0 0.65 1.00 v i zcd,bs input bias current v zcd =1v~5v -1.0 -0.1 1.0 a i zcd,sr source current capability (4) t a =25c -4 ma i zcd,sk sink current capability (4) t a =25c 10 ma t zcd,d maximum delay from zcd to output turn-on (4) dv/dt=-1v/100ns, 5v to 0v 100 200 ns output section v oh output voltage high i o =-100ma, t a =25c 9.2 11.0 12.8 v v ol output voltage low i o =200ma, t a =25c 1.0 2.5 v t rise rising time (4) c in =1nf 50 100 ns t fall falling time (4) c in =1nf 50 100 ns v o,max maximum output voltage v cc =20v, i o =100a 11.5 13.0 14.5 v v o,uvlo output voltage with uvlo activated v cc =5v, i o =100a 1 v restart / maximum switching frequency limit section t rst restart timer delay 50 150 300 s f max maximum switching frequency (4) 250 300 350 khz rdy pin (fl7930c only) i rdy,sk output sink current 1 2 4 ma v rdy,sat output saturation voltage i rdy,sk = 2ma 320 500 mv i rdy,lk output leakage current output high impedance 1 a soft-start timer section t ss internal soft-soft (4) 3 5 7 ms protections v ovp,inv ovp threshold voltage at inv pin t a =25c 2.620 2.675 2.730 v hy ovp,inv ovp hysteresis at inv pin t a =25c 0.120 0.175 0.230 v v ovp,ovp ovp threshold voltage at ovp pin (fl7930b only) t a =25c 2.740 2.845 2.960 v hy ovp,ovp ovp hysteresis at ovp pin (fl7930b only) t a =25c 0.345 v v en enable threshold voltage 0.40 0.45 0.50 v hy en enable hysteresis 0.05 0.10 0.15 v t sd thermal shutdown temperature (4) 125 140 155 c t hys hysteresis temperature of tsd (4) 60 c note: 4. these parameters, although guaranteed by design, are not production tested.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fl7930 ? rev. 1.0.0 8 fl7930 ? single-stage flyback and bou ndary-mode pfc controller for lighting comparison of fl6961, fl7930b, and fl7930c function fl6961 fl7930b fl7930c advantages ovp pin none integrated none ? no external circuit for additional ovp ? reduced power loss and bom cost due to additional ovp circuit pfc ready pin none none integrated ? no external circuit for pfc output uvlo ? reduced power loss and bom cost due to pfc out uvlo circuit ? versatile open-drain pin frequency limit none integrated integrated ? abnormal ccm operation prohibited ? abnormal inductor current accumulation can be prohibited ac absent detection none integrated integrated ? increased system reliability with ac on-off test ? guaranteed stable operatio n at short electric power failure soft-start and startup without overshoot none integrated integrated ? reduced voltage and current stress at startup ? eliminates audible noise due to unwanted ovp triggering control range compensation none integrated integrated ? can avoid burst operation at light load and high input voltage ? reduced probability of audible noise due to the burst operation thd optimizer external internal internal ? no external resistor is needed tsd none integrated integrated ? stable and reliable tsd operation ? converter temperature range limited range comparison of fl7930b and fl7930c function fl7930b fl7930c remark rdy pin none integrated ? user choice for the use of pin #2 fl7930b : ovp fl7930c : rdy ovp pin integrated none control range compensation integrated integrated
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fl7930 ? rev. 1.0.0 9 fl7930 ? single-stage flyback and bou ndary-mode pfc controller for lighting typical performance characteristics figure 7. v oltage feedback input threshold 1 (v ref1 ) vs. t a figure 8. start threshold voltage ( v start ) vs. t a figure 9. stop threshold voltage ( v stop ) vs. t a figure 10. startup supply current (i start ) vs. t a figure 11. operating supply current (i op ) vs. t a figure 12. output upper clamp voltage (v eah ) vs. t a
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fl7930 ? rev. 1.0.0 10 fl7930 ? single-stage flyback and bou ndary-mode pfc controller for lighting typical performance characteristics figure 13. zero duty cycle output voltage (v eaz ) vs. t a figure 14. maximum on-time program 1 (t on,max1 ) vs. t a figure 15. maximum on-time program 2 (t on,max2 ) vs. t a figure 16. current sense input threshold voltage limit (v cs ) vs. t a figure 17. input high clamp voltage ( v clamph ) vs. t a figure 18. input low clamp voltage ( v clampl ) vs. t a
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fl7930 ? rev. 1.0.0 11 fl7930 ? single-stage flyback and bou ndary-mode pfc controller for lighting typical performance characteristics figure 19. output voltage high (v oh ) vs. t a figure 20. output voltage low ( v ol ) vs. t a figure 21. restart timer delay (t rst ) vs. t a figure 22. ovp threshold at ovp pin (v ovp,ovp ) vs. t a figure 23. output saturation voltage (v rdy,sat )vs. t a figure 24. ovp threshold voltage ( v ovp ) vs. t a
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fl7930 ? rev. 1.0.0 12 fl7930 ? single-stage flyback and bou ndary-mode pfc controller for lighting applications information 1. startup : normally, supply voltage (v cc ) of a pfc block is fed from the additional power supply, which can be called standby power. without this standby power, auxiliary winding for zero current detection can be used as a supply source. once t he supply voltage of the pfc block exceeds 12v, internal operation is enabled until the voltage drops to 8.5v. if v cc exceeds v z , 20ma current is sinking from v cc . figure 25. startup circuit 2. inv block : scaled-down voltage from the output is the input for the inv pin. many functions are embedded based on the inv pin: transconductance amplifier, output ovp comparator, an d disable comparator. for the output voltage cont rol, a transconductance amplifier is used instead of the conventional voltage amplifier. the transconductance amplifier (voltage- controlled current source) ai ds the implementation of ovp and disable functions. t he output current of the amplifier changes according to the voltage difference of the inverting and non-inverting input of the amplifier. to cancel down the line input voltage effect on power factor correction, effective contro l response of pfc block should be slower than the line frequency. this conflicts with the transient response of controller. two-pole one- zero type compensation may be used to meet both requirements. the ovp comparator shuts do wn the output drive block when the voltage of the inv pin is higher than 2.675v with 0.175v hysteresis. the disable comparator disables operation when the voltage of the inverting input is lower than 0.35v with 100mv hysteresis. an external small-signal mosfet can be used to disable the ic. the ic operating current decreases to reduce power consumption if the ic is disabled. figure 27 is the timing chart of the internal circuit near the inv pin when rated-pfc output voltag e is assumed at 390v dc and v cc supply voltage is 15v. figure 26. circuit around inv pin figure 27. timing chart for inv block 3. ovp pin : over-voltage protection (ovp) is embedded by the information at the inv pin. that information comes from the output through the voltage dividing resistors. to scale down from high voltage to low voltage, high resistance normally replaced with low resistance. if the resistor of high resistance is damaged and resistance is changed to high, inv pin information is normal, but output voltage exceeds its rated output. once this occurs, output electrolytic capacitor may be damaged. the fl3930b provides an additional ovp pin that can be used to shut down the boost power stage when output voltage exceeds the ovp level if the resistors connected at the inv pin are damaged. to prevent such a catastrophe, an additional ovp pin is assigned to double check output voltage. the additional ovp may be called second ovp, while inv pin ovp can be called the first ovp. since the two ovp conditions are quite different, the protection recovery modes are different.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fl7930 ? rev. 1.0.0 13 fl7930 ? single-stage flyback and bou ndary-mode pfc controller for lighting once the first ovp triggers, switching stops immediately and recovers switching when the output voltage is decreased with a hysteresis. when the second ovp triggers, switching can be recovered only when the v cc supply voltage falls below v stop and builds up higher than v start again and v ovp is lower than hysteresis. if the second ovp is not used, the ovp pin must be connected to the inv pin or to ground. figure 28. comparison of first and second ovp recovery modes 4. rdy output : the fl7930c provides a pfc-ready pin that can be used to tr igger other power stages when pfc output voltage reaches the proper level with hysteresis. when the inv voltage is higher than 2.24v, rdy out is triggered high and lasts until the inv voltage is lower than 2.051v. when input ac voltage is quite high, for example 240v ac , pfc output voltage is always higher than rdy thre shold, regardless of boost converter operation. in this case, the inv voltage is already higher than 2.24v before pfc v cc touches v start . after boost converter operation stops, rdy is not pulled low because the inv voltage is higher than the rdy threshold. when v cc of the pfc drops below 5v, rdy is pulled low even through pfc output voltage is higher than threshold. the rdy pin output is open-drain, so needs an external pull-up resistor to supply the proper power source. the rdy pin output remains floating until v cc is higher than 2v. figure 29. two cases of rdy triggered high figure 30. two cases of rdy triggered low 5. control range compensation : on time is controlled by the output voltage comp ensator. when input voltage is high and load is light, the control range becomes narrow compared to when input voltage is low. that control range decrease is anti- proportional to the double square of the input voltage. thus, at high line, unwanted burst operation can occur at light load and audible noise may be generated from the boost inductor or inductor at input filter. unlike other co nverters, burst operation in pfc block is not needed because the pfc block itself is normally disabled in standby mode. to reduce unwanted burst operation at li ght load, internal control range compensation is implemented and no burst operation occurs until 5% load at high line. 6. zero-current detection : zero-current detection (zcd) generates the turn-o n signal of the mosfet when the boost inductor current reaches zero using an auxiliary winding coupled with the inductor. when the power switch turns on, negative voltage is induced at the auxiliary winding due to the opposite winding direction ( see equation 1 ) and positive voltage is induced (see equation 2) when the power switch turns off. ac ind aux aux v t t v ? ? ? (1) ?? ac pfcout ind aux aux v v t t v ? ? ? (2) where v aux is the auxiliary winding voltage; t ind and t aux are boost inductor turns and auxiliary winding turns, respectively; v ac is input voltage for pfc converter; and v out_pfc is output voltage from the pfc converter. figure 31. circuit near zcd
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fl7930 ? rev. 1.0.0 14 fl7930 ? single-stage flyback and bou ndary-mode pfc controller for lighting because auxiliary winding voltage can swing from negative voltage to positive vo ltage, the internal block in the zcd pin has both posit ive and negative voltage clamping circuits. when the auxiliary voltage is negative, an internal circuit clamps the negative voltage at the zcd pin around 0.65v by sourcing current to the serial resistor between the zcd pin and the auxiliary winding. when the auxiliary voltage is higher than 6.5v, current is sinked through a resistor from the auxiliary winding to the zcd pin. figure 32. auxiliary voltage depends on mosfet switching to check the boost inductor current zero instance, auxiliary winding voltage is used. when boost inductor current becomes zero, there is a resonance between boost inductor and all capacitors at mosfet drain pin, including c oss of the mosfet; an ex ternal capacitor at the d-s pin to reduce the voltage rising and falling slope of the mosfet; a parasitic c apacitor at inductor; and so on to improve performance. resonated voltage is reflected to the auxiliary winding and can be used for detecting zero current of boost inductor and valley position of mosfet voltage st ress. for valley detection, a minor delay by the resist or and capacitor is needed. a capacitor increases the noise immunity at the zcd pin. if zcd voltage is higher than 1.5v, an internal zcd comparator output becomes high and low when the zcd goes below 1.4v. at the falling edge of comparator output, internal logic turns on the mosfet. figure 33. auxiliary voltage threshold when no zcd signal is available, the pfc controller cannot turn on the mosfet, so the controller checks every switching off time and forces mosfet turn on when the off time is longer than 150 s. this is called restart timer. the restart ti mer triggers mosfet turn-on at startup and may be used at the input voltage-zero cross period. s 150 ? figure 34. restart timer at startup because the mosfet turn on depends on the zcd input, switching frequency may increase to higher than several megahertz due to mis-triggering or noise on the nearby zcd pin. if the switching frequency is higher than needed for critical conduction mode (crm), operation mode shifts to continuous conduction mode (ccm). in ccm, unlike crm where the boost inductor current is reset to zero at the next switch on; inductor current builds up at every switching cycle and can be raised to high current that exceeds the current rating of the power switch or diode. this can seriously damage the power switch and result in burn down. to avoid this, maximum switching frequency limitation is embedded. if zcd signal is applied again within 3.3 s after the previous rising edge of the gate signal, this signal is ignored internally and fl7930 waits for another zcd signal. this slightly degrades the power factor performance at light load and high input voltage. figure 35. maximum switching frequency limit operation 7. control : the scaled output is compared with the internal reference voltage and sinking or sourcing current is generated from the comp pin by the transconductance amplifier. t he error amplifier output is compared with the internal sawtooth waveform to give proper turn-on time based on the controller.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fl7930 ? rev. 1.0.0 15 fl7930 ? single-stage flyback and bou ndary-mode pfc controller for lighting figure 36. control circuit unlike a conventional voltage-mode pwm controller, fl7930 turns on the mosfet at the falling edge of zcd signal. on instance is decided by the external signal and the turn-on time lasts until the error amplifier output (v comp ) and sawtooth waveform meet. when load is heavy, output volt age decreases, scaled output decreases, comp voltage increases to compensate low output, turn-on time lengthens to give more inductor turn-on time, and increased inductor current raises the output voltage. this is how pfc negative feedback controller regulates output. the maximum of v comp is limited to 6.5v, which dictates the maximum turn-on time, and switching stops when v comp is lower than 1.0v. s / v 155 . 0 ? figure 37. turn-on time determination the roles of pfc controller ar e regulating output voltage and input current shaping to increase power factor. duty control based on the output voltage should be fast enough to compensate output voltage dip or overshoot. for the power factor, however, the control loop must not react to the fluctuating ac input voltage. these two requirements conflict; ther efore, when designing a feedback loop, the feedback loop should be least ten times slower than ac line frequency. that slow response is made by c1 at compensator. r1 makes gain boost around operation region and c2 attenuates gain at higher frequency. boost gain by r1 helps raise the response time and improves phase margin. figure 38. compensators gain curve for the transconductance error amplifier side, gain changes based on differential input. when the error is large, gain is large to force the output dip or peak to suppress quickly. when the error is small, low gain is used to improve power factor performance. mho 250 ? mho 115 ? figure 39. gain characteristic 8. soft-start : when v cc reaches v start , an internal reference voltage is increased like a stair step for 5ms. as a result, v comp is also raised gradually and mosfet turn-on time increases smoothly. this reduces voltage and current stress on the powe r switch during startup. v ref ss g m v inv =0.4v i source comp v comp i source comp r comp =v comp t (v ref ss -v inv )g m =i source comp v ref end =2.5v fl7930 rev.00 5ms v cc v start =12v figure 40. soft-start sequence
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fl7930 ? rev. 1.0.0 16 fl7930 ? single-stage flyback and bou ndary-mode pfc controller for lighting 9. startup without overshoot: feedback control speed of pfc is quite slow. due to the slow response, there is a gap between out put voltage and feedback control. that is why over-v oltage protection (ovp) is critical at the pfc contro ller and voltage dip caused by fast load changes from light to heavy is diminished by a bulk capacitor. ovp is easily triggered during startup phase. operation on and off by ovp at startup may cause audible noise and can increase voltage stress at startup, which is normally higher than in normal operation. this operation is better when soft-start time is very long; however, too much startup time enlarges the output voltage building time at light load. fl7930 has less overshoot prevention at st artup. during startup, the feedback loop is controlled by an internal proportional gain controller. when the ou tput voltage reaches the rated value, it switches to an external compensator after a transition time of 30ms. in short, an internal proportional gain controller eliminates overshoot at startup and an external conventional compensator takes over successfully afterward. figure 41. startup with overshoot prevention 10. thd optimization : total harmonic distortion (thd) is the factor that dictates how closely the input current shape matches sinusoidal form. the turn-on time of the pfc controller is almost c onstant over one ac line period due to the extremely low feedback control response. the turn-off time is determined by the current decrease slope of the boost inductor made by the input voltage and output voltage. once inductor current becomes zero, resonance between c oss and the boost inductor makes oscillating waveforms at the drain pin and auxiliary winding. by checking the auxiliary winding voltage through the zcd pin, the controller can check the zero current of the boost inductor. at the same time, a minor delay is inserted to determine the valley position of drain voltage. the input and output voltage difference is at its maximum at the zero -cross point of the ac input voltage. the current decreas e slope is steep near the zero-cross region and more negative inductor current flows during a drain voltage valley-detection time. such a negative inductor current cancels down the positive current flows and input current becomes zero, called ?zero-cross distortion? in pfc. figure 42. input and output current near input voltage peak figure 43. input and output current near input voltage peak zero cross to improve this, lengthened turn-on time near the zero- cross region is a well-known technique, though the method may be different from company to company and may be proprietary. fl7930 accomplishes this by sourcing current through the zcd pin. auxiliary winding voltage becomes negative when the mosfet turns on and is proportional to input voltage. the negative clamping circuit of zcd outputs the current to maintain the zcd voltage at a fixed value. the sourcing current from the zcd is directly proportional to the input voltage. some portion of this current is applied to the internal sawtooth generator, together with a fixed- current source. theoretically , the fixed-current source and the capacitor at sawtooth generator decide the maximum turn-on time when no current is sourcing at zcd clamp circuit and available turn-on time gets shorter proportional to the zcd sourcing current.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fl7930 ? rev. 1.0.0 17 fl7930 ? single-stage flyback and bou ndary-mode pfc controller for lighting figure 44. circuit of thd optimizer figure 45. effect of thd optimizer by thd optimizer, turn-on time over one ac line period is proportionally changed, depending on input voltage. near the zero cross, lengthened turn-on time improves thd performance. 11. input voltage absent detection : to save power loss caused by input voltage-sensing resistors and to optimize thd, fl7930 omits ac input voltage detection. therefore, no information about ac input is available from the internal controller. in many cases, the v cc of pfc controller is supplied by an independent power source, like standby power. in this scheme, some mismatch may exist. for example, when the electric power is suddenly interrupted during two or three ac line periods; v cc is still alive during that time, but output voltage drops because there is no input power source. consequently, the control loop tries to compensate for the output voltage drop and v comp reaches its maximum. this lasts until ac input voltage is live again. when ac input voltage is live again, high v comp allows high switching current and more stress is put on the mosfet and diode. to protect against this, fl7930 internally checks if the input ac voltage exists. if input does not exist, soft-start is reset and waits until ac input is live again. soft-start manages the turn-on time for smooth operation when it det ects ac input is applied, which applies less voltage and current stress on startup. figure 46. operation without input voltage absent circuit figure 47. operation with input voltage absent circuit
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fl7930 ? rev. 1.0.0 18 fl7930 ? single-stage flyback and bou ndary-mode pfc controller for lighting 12. current sense : the mosfet current is sensed using an external sensing resistor for the over-current protection. if the cs pin voltage is higher than 0.8v, the over-current protection comparator generates a protection signal. an internal rc filter of 40k ? and 8pf is included to filter switching noise. 13. gate driver output : fl7930 contains a single totem-pole output stage designed for a direct drive of the power mosfet. the drive output is capable of up to +500/-800ma peak current with a typical rise and fall time of 50ns with 1nf load. the output voltage is clamped to 13v to protect the mosfet gate even if the v cc voltage is higher than 13v. 14. pcb layout pfc block normally handles high switching current and the voltage low-energy signal path can be affected by the high-energy path. cauti ous pcb layout is mandatory for stable operation. ? the gate drive path should be as short as possible. the closed-loop that star ts from the gate driver, mosfet gate, and mosfet source to ground of pfc controller is recommended as close as possible. this is also the crossing point between power ground and signal ground. power ground path from the bridge diode to the output bulk capacitor should be short and wide. the sharing position between power ground and signal ground should be only at one position to avoid ground loop noise. signal path of pfc controller should be short and wide for external components to contact. ? pfc output voltage sensing resistor is normally high to reduce current c onsumption. this path can be affected by external noise. to reduce noise possibility at the inv pin, a shorter path for output sensing is recommended. if a shorter path is not possible, place some dividing resistors between pfc output and the inv pin ? closer to the inv pin is better. relative high vo ltage close to the inv pin can be helpful. ? zcd path is recommended close to auxiliary winding from boost inductor and to the zcd pin. if that is difficult, place a small capacitor (below 50pf) to reduce noise. ? switching current-sense path should not share with any other path to avoid interference. some additional components may be needed to reduce the noise level applied to the cs pin. ? a stabilizing capacitor for v cc is recommended as close as possible to the v cc and ground pins. if it is difficult, place the smd capacitor as close to the corresponding pins as possible. figure 48. recommended pcb layout
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fl7930 ? rev. 1.0.0 19 fl7930 ? single-stage flyback and bou ndary-mode pfc controller for lighting physical dimensions figure 49. 8-lead small outline package (sop) package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . 8 0 see detail a notes: unless otherwise specified a) this package conforms to jedec ms-012, variation aa, issue c, b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern sta ndard: soic127p600x175-8m. e) drawing filename: m08arev13 land pattern recommendation seating plane c gage plane x 45 detail a scale: 2:1 pin one indicator 4 8 1 b 5 a 5.60 0.65 1.75 1.27 6.20 5.80 3.81 4.00 3.80 5.00 4.80 (0.33) 1.27 0.51 0.33 0.25 0.10 1.75 max 0.25 0.19 0.36 0.50 0.25 r0.10 r0.10 0.90 0.40 (1.04) option a - bevel edge option b - no bevel edge 0.25 cba 0.10 c
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fl7930 ? rev. 1.0.0 20 fl7930 ? single-stage flyback and bou ndary-mode pfc controller for lighting

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